`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company: University of Utah
// Engineer: David Hurst, Tyson Hunt, Chase Hochstrasser
//
// Create Date:   15:51:05 09/20/2011
// Design Name:   Counter
// Module Name:   C:/Users/Chase/16bitcpu/CounterTest.v
// Project Name:  CPU
// Target Device:  
// Tool versions:  
// Description: Test if the counter is counting up and resets if active.
//
// Verilog Test Fixture created by ISE for module: Counter
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:	
// 
////////////////////////////////////////////////////////////////////////////////

module CounterTest;

	// Inputs
	reg Clock;
	reg CLEAR;

	// Outputs
	wire [15:0] Data_Output;

	// Instantiate the Unit Under Test (UUT)
	Counter uut (
		.Clock(Clock), 
		.CLEAR(CLEAR), 
		.Data_Output(Data_Output)
	);

	initial begin
	
		// Initialize Inputs
		Clock = 0;
		CLEAR = 0;

		// Wait 100 ns for global reset to finish
		#100;
        
		// Add stimulus here
		//$monitor("Clock = %d CLEAR%d Data_Output =%d",Clock, CLEAR, Data_Output);
	
		
		#200 // Wait 200 ns
		CLEAR = 1; // Reset is active
		
		#10 // Wait 10 ns
		
		CLEAR = 0; // Reset is NOT active
		
	end
	
	// Always block
	always
		begin
		#1 // Wait 1 ns
		Clock = ~Clock; // Clock is not Clock
		end
      
endmodule

